Seed - layer deposition Patterning Insulator deposition and patterning Seed - layer deposition Seed layer Substrate

Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 199Os, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call zyxwvutsrqponmlkjihgfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system. Introduction zyxwvutsrqponmlkjihgfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA The advantages of Cu relative to AI(Cu) for chip wiring, which include lower resistance, higher allowed currcnt density, and increased scalability [l-31, have long been recognized. Copper metallization of chips has thus been the subject of intense investigation for more than a decade [ l , 4, 51. In 1997, IBM published results [ I ] from fully integrated devices with Cu interconnections that showed a 40-45% drop in the resistance of claddcd Cu wiring compared to AI(Cu) wiring, and a substantial improvement in electromigration resistance. A paper on Cu interconnections was also published by Motorola [6]. We have developed electroplating technology for copper that has been successfully implemented in IBM for the fabrication of chip interconnect structures [7, 81. A summary of milestones of damascene electroplating for Cu chip interconnections in IBM appears in zyxwvutsrqponmlkjihgfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA Table 1. In this paper we discuss aspects of the plating process in relation to a method of integration called damascene (or dual damascene). We show that under certain conditions, electroplating inside trenches occurs preferentially in the bottom, leading to void-free deposits. We call this phenomenon zyxwvutsrqp mlkjihgfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA superfilling. We present a mathematical model of superfilling based on the assumptions that additives-compounds added in Cu plating solutions to improve deposit properties-are consumed on the wafer surface and suppress the kinetics of Cu deposition. Since interior locations of trenches are less accessible to additives, less suppression of the reaction kinetics occurs there, causing higher deposition rates. Superfilling seems to be a unique property o f electroplating, which is therefore a particularly suitable technology for the fabrication of Cu chip interconnections.